NEWS & EVENTS
FOGALE nanotech acquired ALTATECH
On April 15, 2016
A leader in advanced metrology solutions for semiconductor manufacturing, acquired ALTATECH Delivering leading-edge full process control tools and software for advanced semiconductor manufacturing & enabling more than Moore to become a reality
Nimes, France, April 15, 2016 - FOGALE nanotech today announced that it has acquired Altatech, a specialized technology leader in the development of wafer inspection and material deposition tools for semiconductor manufacturing. Altatech SAS has headquarters in Grenoble, France, located in the center of the French Silicon Valley with a commercial subsidiary in Germany.
This strategic acquisition uniquely positions Fogale nanotech to provide the full range of inspection and metrology tools to address high throughput 2D, 3D and full wafer inspection for 3D IC TSV, advanced packaging, MEMS, LED and Substrate applications.
It offers a strong operational capability to better serve our clients through a complementary portfolio of products and solutions in the field of Advanced Semiconductors. Commenting on this announcement, Patrick Leteurtre, Chief Executive Officer of FOGALE nanotech, said: “ The Altatech acquisition is superbly aligned with Fogale nanotech group’s strategy to incubate, develop and accelerate commercial and industrial growth of product subsidiaries. Altatech brings its own innovative technologies and products to address the growing advanced semiconductor manufacturing market which will become mainstream following support announced by major semiconductor product leaders.”
The Board of Fogale nanotech has unanimously approved this transaction.
By leveraging Fogale nanotech’s strong portfolio of products and customers, the combined comprehensive solution will lead to additional sales, and reinforce Fogale nanotech’s position as a key player in the fast-growing inspection and metrology process control market for advanced semiconductor back-end manufacturing.
Thanks to this acquisition&rbquo; new synergies will:
-Support the development and production of the most advanced technologies for both front end and mid/back-end applications, with a focus on customer yield improvement,
- Bring necessary critical mass and strong financial strength to drive leadership positioning in the demanding metrology, inspection and deposition business for the semiconductor manufacturing industry,
- Create an extensive, high quality intellectual property and technology portfolio, in line with Fogale nanotech’s long-term strategy to expand its in house technologies and its own IP portfolio,
- Expand Fogale nanotech’s customer base in the advanced semiconductor manufacturing industry.
At closing, Fogale nanotech paid a fixed price in cash in consideration for 100% of the shares of Altatech SAS.
Created in 2004, Altatech offers a unique portfolio of technologies and equipment for mature and holistic defect inspection. It develops smart, highly efficient and cost-effective inspection and chemical vapor deposition (CVD) technologies used for manufacturing of semiconductors, LEDs, MEMS and photovoltaic devices.
On December 16-18 2015 / Booth: 3132
Visit APPEX – our exclusive distributor at Semicon Japan 2015 at their booth to consult your metrology demand. We are glad to share FOGALE’s rich experiences of inspection and metrology solutions in 3DIC, FOWLP, MEMS process control. More information : www.semiconjapan.org/en/ & www.appex.co.jp
On October 6-8 2015 / booth: 2018
European MEMS Summit 2015
17-18 September - Milan, Italy
Visit our booth. FOGALE Nanotech is delivering inspection and metrology solutions for MEMS. Surface topography, tomography and defect review solutions are mandatory to keep MEMS manufacturing yield at the highest level. Metrology: TSV, High A/R trenches, bonded substrates thicknesses, Through cap membrane deflection, MEMS in motion analysis and more Inspection: Defect review, IR inspection for buried defect, Bonding interface analysis…..
On June 17-18 2015 / booth N°515
In San Francisco on July 14-16 / booth 2317 / south hall
EMRS conference in Strasbourg
FOGALE invites you to EMRS conference in Strasbourg on May 15th at 9h45 for Optical Characterization and Defect inspection for 3D stacked IC technology : www.emrs-strasbourg.com Optical Characterization and Defect inspection for 3D stacked IC technology Authors : J.Ph.Piel, G.Fresquet , G.Ribette, S.Perrot, Y.Randle, D.Lebellego, S.Petitgrand Affiliations : FOGALE Nanotech, 125 Rue de l'Hostellerie-Bat.A, 30900 Nîmes, France Tel: 33 (0) 466 620 555 / Mail : firstname.lastname@example.org Resume : Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes. To increase the development speed, it is a big advantage to have metrology and defect inspection on the same platform. A flexible tool, equipped with multi sensors and multi-technologies to cover different types of measurements broadband, is more versatile to face the different steps of the current and future complex manufacturing process. A detailed presentation of the tool illustrated by main applications will be presented in this paper. 3D IC devices utilize TSVs for direct interconnect. The depth, top and bottom CD (critical diameter) of such TSVs, with a diameter as small as 5 µm with a high aspect ratio, are characterized. During wafer temporary bonding, which is an handling technique that allows wafer thinning with a thickness of less than 100 µm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass. After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined. After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed. Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate. In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow to characterize specifically with an excellent sensitivity, the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing, it will be detailed and results will be presented to illustrate the possibilities of this new inspection technic.
Minapad 2015 Grenoble
Grenoble, April 22 23, 2015 IMAPS-France Micro/Nano-electronics Packaging and Assembly, Design and manufacturing Forum. MiNaPAD Conference is the major electronics packaging, interconnection and integration conferences of France, and will be held at the WTC (World Trade Center). Visit our booth at Minapad.
3D European Summit
20-21 January 2015
SEMI Europe is proud to announce the 3rd edition of the European 3D TSV Summit. The event will be held on January 19-21, 2015 in Grenoble (France). Please visit FOGALE booth at Minatec. Visit our booth!
Fogale will present Memscan and T-MAP DUAL 3D capabilities for 3DIC and MEMS:
High A/R Trench and TSV CD and depth
Defect review and inspection
Thickness, Bow and Warp
Stack substrates Thickness and TTV
Overlay and registration: in plane and out of the plane
Front to back registration
WLP, Wafer level Packaging process control
Surface shape, Membrane thickness, membrane shape and more…