3D IC TSV
Bringing 3D to production requires thorough process control in order to insure technically and economically competitive manufacturing.
3D integration of electronic systems can be addressed in many different ways and a large variety of through-Si via (TSV) technologies is being proposed. These approaches can be categorized by the place of the 3D interconnects in the interconnect hierarchy. The TSV approaches roughly fall into two categories: TSVs addressing interconnects at the bond pad level (Via last) and interconnects at the level of on-chip electrical wiring (Via first or middle).
The 3D integration process is pushing demand for ultra-thin semiconductor wafers. As wafer thickness decreases to 100µm and below, manufacturing challenges arise especially for 200 and 300 mm wafers. Ultra-thin wafers are less stable and more vulnerable to stresses, and die can be prone to breaking and warping - not only during grinding but also at subsequent processing steps. To address these challenges, temporary wafer carriers were developed to support the wafer during backgrinding and subsequent post-thinning processes. The thinning process requires thickness and TTV measurement of the stack substrate and of the silicon individual layer at the same time.
- TSV formation
- Wafer on temporary bonding: ttv, bow, void detection, exentricity…
- Wafer thinning: rst, edge trim, µcrack detection, stress, defect review…
- TSV reveal: nails height and coplanarity
- Stacking: cmp control, bonding process control
- Wafer on dicing frame inspection capability
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